Some good OCP talks
AMD Keynote: CPU TAM, Helios shipments and the new agentic rack
Lisa Su (Chair & CEO, AMD).NVIDIA Keynote: Rubin deployment, dedicated CPU racks and optical NVLink
Ian Buck (VP, Hyperscale & High-Performance Computing, NVIDIA).Meta Networking: Ethernet scale-up, merchant switches and multi-building training
Omar Baldonado (Director of Engineering, Meta).Credo: The optical roadmap beyond active electrical cables
Bill Brennan (President & CEO, Credo).Compute Meets Optics: OpenAI’s architecture and the path into scale-up
Binbin Guan (Member of Technical Staff, OpenAI); Manish Mehta (VP, Marketing & Operations, Broadcom); Tareq Bustami (VP, Market Technology, Celestica).Astera Labs: Orion, rack-scale connectivity and a dedicated KV-cache tier
Chris Petersen (VP & Technologist, Astera Labs); Dimitris Ziakas (CTO & VP, Architecture, Hyve Solutions).Google: 800V power, batteries, liquid cooling and flexible grid access
Tom Garvens (VP, Hardware Platform Engineering, Google Cloud); Amber Huffman (Technologist, AI & Infrastructure, Google).Microsoft: Getting more compute from the power already available
Brijesh Warrier (VP, Software Engineering, Microsoft); Nithish Mahalingam (Partner Director of Engineering, Microsoft).Meta Keynote: Building and operating a gigawatt-scale training cluster
Santosh Janardhan (Head of Infrastructure, Meta).Broadcom Keynote: Ethernet adoption and why copper lasts longer
Asad Khamisy (SVP & GM, Core Switching Group, Broadcom).Arm Keynote: Three CPU markets inside the AI data center
Mohamed Awad (EVP & GM, Cloud AI Business Unit, Arm).AMD Helios Technical: Memory, integrated networking and rack-level co-design
Andrew Dieckmann (Corporate VP & GM, AMD); Steve Scott (Corporate Fellow, AMD); Alan Smith (Corporate Fellow, AMD).Nokia: AI networking beyond the data center
Clayton Wagar (Principal Consulting Engineer, Nokia).Marvell / Microsoft / Oracle: Moving hardware security into every compute node
Cary Ussery (SVP & GM, Multimarket Business Group, Marvell); Mohan Kumar (Architecture & Ecosystems, Oracle Cloud Infrastructure); Jayant Gandhi (Security Architect, Microsoft Azure).
1. AMD Keynote: A much larger CPU opportunity, Helios entering production and a separate rack for agents
Speaker: Lisa Su, Chair & CEO, AMD.
Summary: AMD’s most consequential claims were that its CPU TAM estimate has been raised three times in nine months and now exceeds $200B by 2030, and that Helios production shipments started in September. The new Helion rack turns the agentic-CPU thesis into a product, while Verano extends the CPU roadmap toward lower-power, memory-intensive configurations.
1. The CPU market is being redefined by agent execution, not just GPU hosting
Su put the data-center AI accelerator opportunity at approximately $1.5T by 2030, but the sharper change was CPUs: AMD now sees a market exceeding $200B by 2030, growing at roughly a 50% CAGR over the next several years. These are AMD’s market forecasts, not Street estimates.
The underlying argument is that agents create substantial work outside model inference: executing code, querying applications, managing context and coordinating other agents. That adds a CPU workload alongside the processors already supporting GPUs. The keynote’s older ~$20B market characterization should not be treated as a directly comparable starting point for the new CAGR.
2. Helios has moved from launch to initial customer deployment
Su said production shipments began in September, with the ramp continuing through Q4 and 1H27. AMD said initial systems are installed and running at OpenAI, Meta, Microsoft and Oracle, with deliveries, deployments and workload validation underway.
That is a meaningful execution milestone, but initial installations are not equivalent to completing the previously announced multi-gigawatt commitments. The next question is the pace at which those installations convert into repeatable, large-scale deployment.
3. Helion targets a different workload from Helios
Helion is designed around agentic execution, with CPU-heavy configurations for hyperscalers and integrated CPU/GPU configurations for enterprises. AMD’s published specification supports up to 32,768 CPU cores, while an integrated model router sends requests to the appropriate model and compute resources.
The distinction is deliberate: hyperscalers may operate separate inference and agent-execution racks, while an enterprise running smaller models on premises may prefer both functions together. Partner configurations are planned for November 2026. This is a second deployment architecture, not simply a smaller Helios.
4. Verano makes memory and system power part of the CPU debate
AMD showed Verano, a Venice-family EPYC variant optimized for lower system power, with an LPDDR-based memory approach and updated CPU-to-GPU connectivity. Production is planned for 2027.
The important distinction is that AMD is not treating every agent-related CPU workload as a contest for maximum core count. Host processors, dense agent execution and technically demanding agents require different balances of memory bandwidth, connectivity, per-core performance and power.
5. Rack economics depend on the surrounding system
AMD claimed a 30% tokens-per-dollar advantage for Helios, but the keynote did not provide enough comparison detail to extrapolate that advantage across workloads. Its broader engineering argument was more durable: compute, memory capacity, memory bandwidth, networking and software all need to improve together.
The investment implication is twofold: AMD is addressing a larger CPU opportunity while moving its GPU proposition toward a complete deployable system. Neither the TAM forecast nor a vendor benchmark establishes the eventual revenue share or margin contribution.
2. NVIDIA Keynote: Shipping infrastructure today, a larger optical NVLink domain next, and CPUs as a separate product
Speaker: Ian Buck, VP, Hyperscale & High-Performance Computing, NVIDIA.
Summary: NVIDIA combined current Vera Rubin deployment with a preview of a 576-GPU Rubin Ultra NVLink domain using co-packaged optics. Equally important was the dedicated Vera CPU rack for agent execution, plus software and power-management work intended to increase usable compute inside constrained facilities.
1. Separate Vera Rubin deployment from the Rubin Ultra preview
Buck described Vera Rubin as being in production and reaching customer data centers. The subsequent Rubin Ultra preview was a different milestone: a planned 576-GPU NVLink-connected system spanning multiple racks, using a next-generation co-packaged-optics switch tray.
The read-through is that NVIDIA intends to expand the tightly coupled accelerator domain beyond today’s copper-connected rack. The preview supports a future optical-content opportunity, but it should not be counted as a currently shipping 576-GPU configuration.
2. The Vera CPU rack is not merely a GPU accessory
Buck described a dedicated rack containing 256 Vera CPUs for agent execution and related workloads. NVIDIA’s architecture separates its role from the Vera Rubin NVL72 training/inference system: the CPU rack supports tool calling, orchestration and sandboxed execution.
The architectural preference is strong sustained per-core performance, memory access and predictable throughput, rather than optimizing solely for the lowest cost per core. That gives NVIDIA another route into data-center spending, including tasks that do not run directly on its GPUs.
3. Co-packaged optics addresses scale-out first, then larger scale-up domains
Spectrum-X Photonics was presented as a shipping-year scale-out product, while optical NVLink was attached to the next-generation scale-up roadmap. Those are different addressable markets and adoption schedules.
Buck also emphasized multiplane networking and rapid hardware-level failure detection. The economic objective is not simply higher bandwidth: it is avoiding situations where a bad link slows or interrupts a much larger pool of expensive accelerators. His power-efficiency and switch-count improvements were vendor claims tied to particular architectural comparisons.
4. Power management can unlock capacity without a new utility connection
NVIDIA’s MaxLPS discussion focused on the gap between nameplate power and actual workload consumption. If software continuously monitors demand and enforces electrical limits, operators can potentially install or use more compute within the same provisioned power envelope.
This is a utilization opportunity, not the creation of additional electricity. The amount recoverable depends on workload diversity, existing provisioning conservatism and control-system responsiveness. The transcript’s example contained inconsistent figures, so the mechanism is more reliable than a precise fleet-wide uplift.
5. Manufacturing and deployment are becoming part of platform differentiation
Buck contrasted roughly 90 minutes to assemble an earlier compute tray with about one minute for the newer cableless tray design. The comparison concerned a compute tray, not an entire completed rack or commissioned cluster.
The broader MGX contribution standardizes rack, cooling, power and service interfaces. NVIDIA is trying to make manufacturing, installation and servicing repeatable across partners while retaining its system-level co-design advantage. The 800V discussion extends that effort into facilities, rather than assuming every existing data center can accept the next rack unchanged.
3. Meta Networking: Ethernet scale-up is already deployed, and merchant silicon extends across the network
Speaker: Omar Baldonado, Director of Engineering, Meta, overseeing data-center and AI networking.
Summary: The strongest operator disclosure was that Meta’s MTIA 300 already uses Ethernet scale-up based on Broadcom Tomahawk 5, with a Tomahawk 6 design and subsequent ESUN-compliant silicon on the roadmap. Meta also described flatter scale-out fabrics, 102.4T network systems and a new backbone layer built using familiar data-center components.
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