Some good presentations today:
AMD MI455 / Helios System: Steve Scott, David and Krishna, AMD
NVIDIA Vera CPU: Jonathan Evans and Polychronis Sakalakis, NVIDIA
Intel Diamond Rapids Xeon: Krishna, Intel Fellow and Chief Architect for Xeon CPUs
Intel Crescent Island GPU: Sumit and Hongjie, Intel
Waymo Keynote / Physical AI Roadmap: Daniel, Waymo
Waymo Sensor Fusion Processor ASIC: Sabrash and Peter, Waymo
IBM Z Dual-ISA CPU + AI Accelerator: Christian, IBM
Fujitsu Monaka CPU: Fujitsu Monaka architecture team
Intel Wildcat Lake / Core Series 3: Intel Core Series 3 lead SoC architect
BOS Semiconductors Eagle-N Automotive AI Accelerator: K. Ming, BOS Semiconductors
AMD MI455 and the Helios rack-scale AI system
Speakers: Steve Scott, David and Krishna, AMD
Summary: AMD presented Helios as a 72-GPU rack-scale system built around MI455 GPUs, EPYC CPUs, Infinity Fabric and programmable Pensando networking. The focus was memory-semantic Ethernet scale-up, full-rack resilience, liquid cooling and the transition from electrical to optical scale-up.
1. Helios turns 72 MI455 GPUs into one tightly coupled system
Helios consists of 18 nodes, each containing one EPYC CPU and four MI455 GPUs. AMD said the rack delivers almost 1.7 PB/s of aggregate HBM bandwidth, more than 0.25 PB/s per direction across the scale-up network and over 40 TB/s of scale-out bandwidth. The architecture is designed so the full rack behaves like one system rather than a collection of independent servers. AMD uses one CPU per four GPUs, arguing that extensive modeling showed this provides the best price/performance and enough CPU throughput to keep the accelerators fed.
2. AMD is carrying direct memory operations over Ethernet
The MI455 GPUs expose direct loads, stores and atomics across the scale-up pod. AMD packages those memory transactions into Ethernet frames and routes them through AVGO Tomahawk 6 switches, with at most one switch hop required to reach any GPU memory in the rack. Once remote memory is exported and imported into another GPU’s virtual address space, software can access it much like local memory, although with a different performance profile. DMA engines inside the GPUs handle much of the data movement without tying up compute resources.
3. This is likely AMD’s last fully electrical scale-up generation
AMD said Helios is near the practical limit for an all-electrical scale-up fabric. Electrical connectivity forces GPUs, switches and cabling into a very dense physical configuration because reach is limited. AMD expects to begin introducing optical scale-up in the following generation, which should loosen the coupling between the compute topology and rack layout. Optics would allow more physical separation and packaging flexibility, rather than requiring every accelerator and switch to remain packed into one tightly constrained electrical domain.
4. Helios assumes direct liquid cooling, but AMD does not expect a major further jump in rack density
More than 85% of Helios heat is removed through direct liquid cooling, with liquid-cooled compute and switch trays connected through quick disconnects. Asked how rack power evolves, AMD said different data-center operators have different preferred operating ranges, but it does not expect a substantial increase in power density from current levels. The move to optical scale-up should reduce the need to keep pushing physical density simply to preserve signal reach, giving system builders more flexibility in how power and cooling infrastructure are arranged.
5. The Pensando AI NIC is designed around post-deployment programmability
Each GPU can connect directly to multiple 800G Pensando AI NICs, providing up to roughly 2.4 Tb/s of scale-out networking per GPU. AMD deliberately avoided a fixed-function networking design because AI transports, congestion-control methods and telemetry requirements are changing too quickly. The NIC uses programmable packet-processing and DMA pipelines for virtualization, encryption, RDMA transport, load balancing and telemetry. Protocols and congestion algorithms can continue evolving through firmware after the system has already shipped.
6. Multipathing, congestion control and telemetry are becoming part of the accelerator architecture
AMD described spreading one GPU-to-GPU flow across as many as 128 or 256 paths to improve network utilization and avoid low-entropy traffic patterns. The programmable transport can support selective retransmission, remove degraded paths, probe for recovery and implement customer-controlled source routing. Congestion control can react to RTT, packet loss or ECN markers on every packet rather than waiting for a host CPU or driver. Hardware telemetry can track statistics by interface, queue pair or path and stream only the events customers choose to monitor.
7. Full-rack confidential computing and failure isolation are built into the design
AMD said Helios supports confidential computing across the rack using packet-level AES-GCM encryption, device attestation, secure partitioning and protected execution environments. The rack can be divided into virtual pods that provide performance, security and fault isolation. The scale-up fabric is designed to survive the loss of an individual link, switch ASIC or complete switch tray. Traffic is rerouted and lost packets retransmitted automatically, while failed switch trays can be replaced online and brought back into service without shutting down the entire rack.
8. AMD is using Ethernet’s ecosystem while retaining a proprietary transaction layer
AMD’s argument for Ethernet is that it provides mature switches, cables, connectors, management tools and a large supplier ecosystem. The memory transaction protocol above Ethernet is still customized for this use case, with lightweight headers, dynamic packet packing and end-to-end retransmission. AMD distinguished this approach from the consortium-developed UALink protocol: both carry memory transactions, but AMD’s design packetizes them into Ethernet frames and transports them reliably end to end, while UALink uses a different hop-by-hop model.
NVDA Vera CPU for agentic AI
Speakers: Jonathan Evans and Polychronis Sakalakis, NVDA
Summary: NVDA designed Vera around the view that agentic AI makes the CPU a critical part of the inference loop again. The architecture prioritizes high single-thread performance, predictable throughput under load, massive coherent bandwidth and rack-scale confidential computing.
1. Agentic AI turns one query into a full-system workload